![]() ![]() ![]() Verilator supports the more important Verilog 2001 constructs, with additional constructs and Verilog 2005 support added as users request them. It also supports very simple assertions and coverage analysis. Verilator supports the synthesis subset of Verilog, plus initial statements, proper blocking/non-blocking assignments, functions, tasks, multi-dimensional arrays, and signed numbers. However, if you are looking for a path to migrate synthesizable Verilog to C++ or SystemC, and writing just a touch of C code and Makefiles doesn't scare you off, this is the free Verilog compiler for you. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.ĭo not download this program if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator for a little project! Don't get it if you expect a corporate support organization. ![]() It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. Verilator is the fastest free Verilog HDL simulator. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |